Current-mode control (CMC) of a pulse-width-modulated (PWM) buck converter with a duty cycle of more than 50% may enter sub-harmonic oscillations. Lloyd HDixon in References[1]This is discussed in detail in. Dixon said this solution adds a slope to the current-sense signal that is equal to the down-slope of the output Inductor current. This extra voltage needs to be added to the requirement calculation process in order to select the correct current sense resistor.

Push-pull converters, phase-shifted full-bridge converters, or any forward converter with an output inductor duty cycle greater than 50% are some topologies that require this compensation. However, for demonstration purposes, the topology chosen for this article is a relatively unfamiliar one: a three-switch forward converter. See Figure 1 for the basic schematic of the power supply section. Although this topology is patented by TI, it can be used when using TI control ICs in the circuit.

**picture****1 ****Three-Switch Forward Topology**

This topology has many advantages, especially when the input voltage range is 36 to 72 V of a cell phone battery. The topology has a maximum duty cycle of 67%, limiting the design to the maximum duty cycle at 67% of the minimum input voltage. At the same time, the voltage of the main switch when turned off is limited to the power rail input voltage. This means that the low-voltage FET will have a correspondingly low R_{DS}_{(}_{on}_{)}resistors are used together. This topology also provides a way to recover the magnetic energy in the power transformer and primary side leakage inductance, eliminating the need for high loss snubbers.

**picture****2V _{IN(min)}**

**and**

**V**

_{IN(max) }**The maximum load output inductor ripple of**

This converter design is identical to the buck topology in many other respects, but the duty cycle must be limited to 67% to avoid transformer saturation. This limitation can be achieved by choosing a control IC with a programmed maximum duty cycle (eg: UCC2807-1, etc.) (see Reference 2). Since this controller has the required duty cycle limiting function, it is the first choice for this application. Therefore, this paper uses this kind of controller and uses its various characteristics for analysis.

The following analysis assumes a theoretical switching power supply with a 100W, 3.3V output. The maximum peak-to-peak ripple current of this supply through the output inductor is equal to 10% of the maximum output DC load current of 30A, and the input voltage range is between 36V and 78V. Additionally, we also assume a 0.5V forward voltage drop V_{fd }A synchronous rectifier is used for the output. The first step is to determine the turns ratio of the transformer. At minimum input voltage, the duty cycle is at its maximum limit (67%). The voltage required at the output of the transformer can be calculated using the following equation.

If the transformer primary voltage is assumed to be 36V, the turns ratio (Np) is 6.147, so a 6-turn primary would be used. The primary winding is divided into two parts with 3 turns each (see Figure 1). The standard method is to sandwich the secondary winding between two split primary windings, with Q3 also placed between them. With an input of 78V, the transformer output voltage is 12.3V, resulting in a minimum duty cycle D of about 31%_{min}.Therefore, the maximum “off” time is equal to

where f_{sw }The planned switching frequency is 200kHz. The minimum output inductance (L1 shown in Figure 1) to achieve 10% of the ideal peak-to-peak ripple current is:

By calculation, the output inductance in Equation 2 is 4.33 µH. For design convenience, we use 4.5 µH. After using this value, the drop current I of the output inductor can be calculated_{ds}for:

By calculation, the drop current of the inductor (I_{ds}) is 0.844 A/µs.

It is also obtained that the peak current of the output inductor at the maximum input voltage is:

Since the maximum peak-to-peak ripple current is defined as 10% of the output current, this current is balanced to give the rated DC output. The resulting peak current is 31.884 A.

At the minimum input voltage, it is possible to determine the differential voltage of LOUT. From this, we know that the rate of change of the output inductance is 0.489 A/µs. Knowing the duty cycle and frequency, it is possible to calculate the time for the current to increase in the output inductor, and thus to be able to determine the magnitude of the ripple current in these states. Finally, we can know that the peak current at the minimum input voltage is 31.122 A. The specific waveforms are shown in Figure 2. These values are all nearly equal, but if you increase the drop current, they change—in a surprising way. The drop current that must be added to the peak current in order to obtain the maximum input voltage is:

The drop current that must be added to the peak current in order to obtain the minimum input voltage is:

See Figure 3, where the effective drop current is added to the current shown in Figure 2. As a result, the effective peak current for the minimum input voltage is higher than the effective peak current for the maximum input voltage, even though the actual peak values are reversed. The peak value of the effective maximum current (including the drop current from the minimum input voltage) is 33.9A, which is the value that must be used to set the current sense resistor Rs. This current (including the drop current converted to primary current) is 5.658A.

The IC chosen as the controller has a typical current auto-shutoff level of 1.0V, but the tolerance value is between 0.9 and 1.1V. To ensure that all units can deliver the required power, a lower limit is used and the Rs value is set so that it is 95% of the 0.9V minimum at 5.658A. This achieves a 5% transient safety margin and sets Rs at 0.15Ω. Of course, there will be a power loss of around 5W, which is most likely generated by a current transformer. When using a 100:1 transformer, Rs may increase to 15Ω. In the following content, we assume the use of such a transformer.

**picture****3 ****Secondary current plus effective falling current**

In fact, the falling current (I_{ds}) does not flow through neither the current transformer nor the power transformer, but its effect needs to be considered, it affects the resistor R_{s}voltage. Therefore, the resistor R needs to be_{s}and the IC’s current sense pin add a resistor R_{dspri}. At the IC’s current sense pin, a current ramp is injected into the circuit. The presence of this current ramp allows the IC current sense pin and resistor R_{s}between the resistor R_{dspri}The ramp voltage formed in , equal to I_{ds}converted to primary current in resistor R_{s}voltage developed in. We assume that an equivalent falling current is flowing through resistor R_{s}, thus taking into account both the power transformer and current transformer winding ratios. In this case, for calculation simplicity, we set the resistor Rdspri to be 1kΩ, which is much larger than the resistor Rs.

Next, calculate the dv/dt required by Rdspri:

From this result, we can calculate the current ramp required for the 1kΩ resistor:

This current at the maximum “on” time results in a peak current of 70.7 µA.

When using a programmable, maximum duty cycle PWM controller (eg: UCC2807), it is relatively simpler to set the maximum duty cycle to 67% by setting both timing resistors to the same value, as described in the data sheet Show. In addition, the specification of this component is rated, the valley voltage and peak voltage of the timing capacitor are equal to 1/3V_{CC }and 2/3V_{CC}. This gives a 1/3V_{CC }The voltage ramp amplitude. Knowing this, we can now design the circuit to generate a ramp current that can be injected into the current sense circuit to provide a falling current to the current signal.

Figure 4 shows a circuit for generating the desired current. The circuit is based on UCC2807-1 control IC, V_{DD }Set to 11V. The valley and peak voltages of the “triangle” ramp are 3.667V min and 7.33V max, and the min to max time is equal to the maximum “on” time. In this circuit, R3 is equal to 2 times R4. This makes the voltage at the base of Q6 equal to 1/3V_{CC}, which is the valley of the “triangular” voltage. Since the voltage on the “delta” pin is at valley to peak (2/3V_{CC}), the voltage of R2 is between 0 and 1/3V_{CC }linear change between. Choose a value for R2 to get a current of 70.7 µA and a voltage of 3.667 V (51.8 kΩ), then use Q5/R1 and Q7/R6 to build a unified current mirror. This allows the designer to generate the current sense signal, add the desired current to the current sense signal, and have the correct shape and 1KΩ resistor timing.

**picture****4 ****used to generate expectations****R _{dspri }**

**current circuit**

**in conclusion**

The three-switch forward converter has many unique features in energy recovery, it can return the magnetic energy and primary side leakage energy to the source without the use of a snubber, reducing the electromagnetic interference commonly found in ordinary forward converters. It also has many advantages over a two-switch forward topology with a duty cycle greater than 50%. This article presents an example calculation for you. This calculation is necessary when determining the value of the current sense resistor and understanding the effect of the droop current required for stable operation of the buck converter above 50% duty cycle. The article also describes a method to increase the converter’s droop current.

**references**

For more details on this article, please visit www.ti.com/lit/litnumber (replace “litnumber” with the TI document number) to download the Acrobat® Reader® file for the following information.

Document Name TI Document Number

[1]”Current Mode Control of Switch Mode Power Supplies” by Lloyd H Dixon, published in 1985 “TI Power Supply Design Seminar (SEM400)” SLUP075

[2]”Programmable Maximum Duty Cycle PWM Controller”, “UCC1807-x/2807-x/3807-x Product Manual” SLUS163

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